nqdtan

Pinned Repositories

bootgen
bootgen source code
Language:C++00
chisel3
Chisel 3
Language:Scala0 2 00
embeddedsw
Xilinx Embedded Software (embeddedsw) Development
Language:HTML0 0 01
firrtl
Flexible Intermediate Representation for RTL
Language:Scala00
HLS
Vitis HLS LLVM source code and examples
Language:C00
mlir-aie
An MLIR-based toolchain for Xilinx Versal AIEngine-based devices.
Language:C++0 1 01
spades
Language:Verilog3 1 00
vck5000_vivado_ulp
An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000
Language:Tcl6 1 53
vtr7
CS267-SP18 Class Project at UCB
Language:C0 3 00
RapidWright
Build Customized FPGA Implementations for Vivado
Language:Java274 26 244104

nqdtan's Repositories

nqdtan/vck5000_vivado_ulp
An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000
Language:Tcl6 1 53
nqdtan/spades
Language:Verilog3 1 00
nqdtan/bootgen
bootgen source code
Language:C++00
nqdtan/chisel3
Chisel 3
Language:Scala0 2 00
nqdtan/embeddedsw
Xilinx Embedded Software (embeddedsw) Development
Language:HTML0 0 01
nqdtan/firrtl
Flexible Intermediate Representation for RTL
Language:Scala00
nqdtan/HLS
Vitis HLS LLVM source code and examples
Language:C00
nqdtan/mlir-aie
An MLIR-based toolchain for Xilinx Versal AIEngine-based devices.
Language:C++0 1 01
nqdtan/vtr7
CS267-SP18 Class Project at UCB
Language:C0 3 00