openhwgroup/force-riscv

Issues

• I need help about FlatMap

  #86 opened a year ago by kong-ling-hui
  6

• H extension for VS privilege

  #100 opened 4 months ago by kong-ling-hui
  2

• add some H reg ,read memory uninitialized

  #103 opened 2 months ago by xusq123
  0

• DIFFERENCE between EVmRegimeType and EPrivilegeLevelType?

  #101 opened 3 months ago by kong-ling-hui
  6

• how to add a new isa ext like Zba?

  #102 opened 3 months ago by xusq123
  1

• Instruction vmandnot and vmornot have been changed to vmandn and vmorn in Vector Extension Version 1.0

  #99 opened 5 months ago by hcube123
  2

• fail by reinitialize memory range (base,offset,size) = (668,0,4)

  #96 opened 4 months ago by xusq123
  1

• what the difference between priv mode in 3 and (1or 0)

  #98 opened 4 months ago by xusq123
  1

• How to specify a random seed

  #97 opened 6 months ago by xusq123
  2

• Address table overlaps test instructions when generating with very tight memory bounds

  #44 opened 3 years ago by noahsherrill
  7

• What is the role of default preamble sequence

  #93 opened 6 months ago by xusq123
  1

• lui instructions issue

  #94 opened 7 months ago by crystalysj
  3

• If I want to support H Extension, what can I need to do

  #95 opened 7 months ago by kong-ling-hui
  2

• Is there any plan to support hypervisor extension?

  #60 opened 2 years ago by hanfeng0114
  7

• Test register dependency with load/store instructions

  #56 opened 2 years ago by noahsherrill
  10

• where i can find the code for bootloading,in genagentseq

  #92 opened 8 months ago by xusq123
  5

• error found while convert generated elf to binary

  #53 opened 2 years ago by erdevonmatteo11
  7

• Backend APIs for Memory Initialization

  #66 opened a year ago
  4

• Address Error

  #91 opened 10 months ago by kong-ling-hui
  2

• In riscv.ModifierUtils, I didn't found class "AccessFaultModifier"

  #90 opened a year ago by kong-ling-hui
  2

• After 'MRET', generating Privilege mode randomly

  #89 opened a year ago by kong-ling-hui
  3

• After MRET，not the PC I wanted. HELP

  #88 opened a year ago by kong-ling-hui
  10

• Removing support for certain extensions

  #46 opened a year ago by snipppy
  4

• Need help configuring to only generate RV32I

  #80 opened a year ago by saw235
  7

• [fail]Front-end error reported: RuntimeError: Error code: 4

  #79 opened a year ago by superbchetan
  7

• Compilation Errors Occurred Building and Debugging the Project in VSCode

  #81 opened a year ago by gcc-hub
  3

• enhancement needed

  #84 opened a year ago by hanfeng0114
  0

• pybind11 is out of date to support latest python version

  #83 opened a year ago by hanfeng0114
  0

• Build Failed issues

  #82 opened a year ago by Sherleo
  5

• Build Failed at Centos 7.9.2009

  #77 opened a year ago by superbchetan
  5

• Exponential increase in generation time

  #78 opened a year ago by KevinKBytes
  6

• Compilation and simulation issue

  #76 opened a year ago by kobeyu
  8

• No "usage.h" in the compilation

  #74 opened a year ago by baichen318
  5

• handcar_cosim.so is too big

  #72 opened a year ago by hanfeng0114
  3

• Generating C.EBREAK without simulation could make RTL fails to execute test

  #65 opened a year ago by niuqiang-real
  2

• IDE for development

  #67 opened a year ago by KevinKBytes
  6

• AccessFaultModifier not implemented

  #68 opened a year ago by ProssMou
  3

• How to call OvpSimPlus in master_run.py instead of fpix

  #40 opened a year ago by CodeDance364
  3

• Generate a .elf 32 bits is impossible?

  #64 opened a year ago by EdgeOfMemory-cloud
  3

• memory of force-riscv generated elf files

  #70 opened 2 years ago by Imperas
  4

• The configuration file for CVA6 needs update

  #62 opened a year ago
  4

• lr/sc reservation set issue with handcar

  #71 opened 2 years ago by hanfeng0114
  1

• How to override the test termination method of FORCE-RISCV?

  #61 opened 2 years ago
  15

• Update the README to indicate support for Vector 1.0

  #43 opened 3 years ago by MikeOpenHWGroup
  2

• Passing signed values in IMMediates not working

  #58 opened 2 years ago
  5

• bug may exist in page-fault exception handler

  #55 opened 3 years ago by niuqiang-real
  5

• how to generate codes without any physical registers

  #52 opened 3 years ago by erdevonmatteo11
  7

• Parameters used to call genSFENCE seem to be not right

  #47 opened 3 years ago by niuqiang-real
  8

• "action_code_reg_val" was pushed into DataBlock twice

  #48 opened 3 years ago by niuqiang-real
  1

• Use custom memory mapping

  #42 opened 3 years ago by Wlgen
  4