/LiteX_Reference_Design_rs

System Level Design created using LiteX infra, target platform are ARTY A7, basys 3 fpga

Primary LanguageVerilogMIT LicenseMIT

LiteX_Reference_Design

System Level Design created using LiteX infra, target platform are ARTY A7, basys 3 fpga.

Raptor designs will be added in the future.