Pinned Repositories
1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
FOEDAG
Framework Open EDA Gui
FOEDAG_rs
Raptor's GUI
GettingStartedWithFPGAs
Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.
IP_Catalog
IP Catalog for Raptor.
open-source-fpga-resource
A list of resources related to the open-source FPGA projects
project-ideas
An area to track open-source project ideas of interest to OSFPGA.
Raptor
Raptor end-to-end FPGA Compiler and GUI
Virtual-FPGA-Lab
This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.
yosys_verific_rs
Yosys + (Optional) Verific Integration
The Open-Source FPGA Foundation's Repositories
os-fpga/1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
os-fpga/Virtual-FPGA-Lab
This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.
os-fpga/Raptor
Raptor end-to-end FPGA Compiler and GUI
os-fpga/FOEDAG
Framework Open EDA Gui
os-fpga/FOEDAG_rs
Raptor's GUI
os-fpga/IP_Catalog
IP Catalog for Raptor.
os-fpga/RTL_Benchmark
This repository contains the benchmarks.
os-fpga/yosys_verific_rs
Yosys + (Optional) Verific Integration
os-fpga/Backend
Compiler backend from packing to bitstream generation.
os-fpga/device_modeling
os-fpga/FPGA_PRIMITIVES_MODELS
os-fpga/openocd
Official OpenOCD Read-Only Mirror (RapidSilicon Forked)
os-fpga/Validation
Raptor Compiler Validation tests
os-fpga/zephyr-rapidsi-dev
os-fpga/ArchBench
Architecture file validation testcase - RTL to Bitstream simulation flow
os-fpga/axi_i2c_bridge
os-fpga/post_build_artifacts
os-fpga/rapid_power_estimator
Rapid Power Estimator For Raptor
os-fpga/Raptor_Tools
os-fpga/yosys_rs
Raptor's Yosys hard fork. Contains optimizations
os-fpga/Jira_Testcase
os-fpga/litex_reference_designs
Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.
os-fpga/logic_synthesis-rs
os-fpga/yosys-rs-plugin
Rapidsilicon's Yosys Plugin
os-fpga/abc-rs
os-fpga/raptor_downloader
os-fpga/tcl
The Tcl Core. (Mirror of core.tcl-lang.org)
os-fpga/testlic1
os-fpga/testPR
os-fpga/zephyr_rs
Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.