p3da

Pinned Repositories

dummy_vip
Files for the IP Integration Exercise
Language:SystemVerilog00
esp_bd
0 1 00
pulp-runtime
Simple runtime for Pulp platforms
Language:C00
pulp-runtime-examples
Examples for pulp-runtime
Language:C00
pulp_eth_app
Language:Stata00
pulp_soc
Language:SystemVerilog00
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Language:C++0 0 00
pulpissimo-assets
Language:SystemVerilog0 1 00
pulpissimo-wide-alu
Language:SystemVerilog00
verilog-ethernet_ptp
Language:Verilog50

p3da's Repositories

p3da/verilog-ethernet_ptp
Language:Verilog50
p3da/dummy_vip
Files for the IP Integration Exercise
Language:SystemVerilog00
p3da/esp_bd
0 1 00
p3da/pulp-runtime
Simple runtime for Pulp platforms
Language:C00
p3da/pulp-runtime-examples
Examples for pulp-runtime
Language:C00
p3da/pulp_eth_app
Language:Stata00
p3da/pulp_soc
Language:SystemVerilog00
p3da/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Language:C++0 0 00
p3da/pulpissimo-assets
Language:SystemVerilog0 1 00
p3da/pulpissimo-wide-alu
Language:SystemVerilog00
p3da/udma_eth_frame
Language:SystemVerilog
p3da/udma_ptp_ts
pulpissimo udma peripheral for ptp timestamps
Language:SystemVerilog
p3da/verilog-ethernet
Verilog Ethernet components for FPGA implementation
Language:Verilog0 0
p3da/wide_alu_ip
p3da/wide_alu_ipV2
Language:SystemVerilog