Pinned Repositories
caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
caravel_aes_accelerator
caravel_user_project-gf180mcu
caravel_user_project_analog
caravel_user_project_example
counter_caravel_example
https://caravel-user-project.readthedocs.io
IP_Utilities
AUC Open Hardware Lab (AUCOHL) IP Utilities
mpc
Multi-Project Support for Caravel
open_pdks
PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
passant5's Repositories
passant5/caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
passant5/caravel_aes_accelerator
passant5/caravel_user_project-gf180mcu
passant5/caravel_user_project_analog
passant5/caravel_user_project_example
passant5/counter_caravel_example
https://caravel-user-project.readthedocs.io
passant5/IP_Utilities
AUC Open Hardware Lab (AUCOHL) IP Utilities
passant5/mpc
Multi-Project Support for Caravel
passant5/open_pdks
PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.
passant5/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.