/dynamic-pattern-detector-verilog

A project to implement and test dynamic pattern detector using verilog in different ways.

Primary LanguageVerilog

Dynamic pattern detector using verilog

A project to implement and test dynamic pattern detector using verilog in different ways.

  • Dynamic pattern detector with variable number of bits in implicit style fsm.
  • Dynamic 3 bit pattern detector in explicit style fsm.

Files

  1. Implicit fsm design and testbench
  2. Explicit fsm design and testbench