J1: a small Forth CPU Core for FPGAs
Rewritten in SystemVerilog from Verilog Source.
ModelSim Altera Starter Edition 10.1d compiles and simulates with unions. Quartus II for Cyclone II FPGA cannot use them. Use this as a workaround.
J1: a small Forth CPU Core for FPGAs
Rewritten in SystemVerilog from Verilog Source.
ModelSim Altera Starter Edition 10.1d compiles and simulates with unions. Quartus II for Cyclone II FPGA cannot use them. Use this as a workaround.