Issues
- 0
Unbreak build and CI
#29 opened by peteut - 1
I would like use it with PYNQ board
#16 opened by kdpatino - 1
Migen platform compatibility
#13 opened by sbourdeauducq - 0
- 0
typo in soc_core.py
#14 opened by sbourdeauducq - 0
Channels Should be Stream Interfaces
#12 opened by peteut - 0
High-Speed DMA Controller Peripheral
#11 opened by peteut - 4
misoc.interconnect.stream -> DMAC | PRI
#6 opened by peteut - 0
Add Documentation
#10 opened by peteut - 0
Expose `dma[:].rst_n` from `PS7`
#9 opened by peteut - 3
- 2
- 2
Add AXI4-Lite Bridge Module
#1 opened by peteut - 1
AXI2CSR W/ 16 Bits Bus
#4 opened by peteut - 0
CSR Shall Be Word Aligned
#5 opened by peteut - 3
DT Overlay Generator
#3 opened by peteut - 0
Tests for AXI2CSR
#2 opened by peteut