pierregobin

pierregobin's Stars

• janestreet/hardcaml

  Hardcaml is an OCaml library for designing hardware.

  Language:OCaml62639

• sylefeb/Silice

  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

  Language:C++1.3k78

• mosscomp/moss

  A computer for human beings.

  Language:Tcl402

• bl0x/learn-fpga-amaranth

  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL

  Language:Python8211

• trabucayre/openFPGALoader

  Universal utility for programming FPGA

  Language:C++1.1k234

• amaranth-lang/amaranth

  A modern hardware definition language and toolchain based on Python

  Language:Python1.5k168

• proteus-core/proteus

  The SpinalHDL design of the Proteus core, an extensible RISC-V core.

  Language:Scala378

• radareorg/radare2

  UNIX-like reverse engineering framework and command-line toolset

  Language:C20k3k

• openhwgroup/cv32e40x

  4 stage, in-order, compute RISC-V core based on the CV32E40P

  Language:SystemVerilog19649

• openhwgroup/cv32e41p

  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

  Language:SystemVerilog2711

• openhwgroup/cve2

  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

  Language:SystemVerilog2619

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3k734

• jart/blink

  tiniest x86-64-linux emulator

  Language:C6.8k216

• wavedrom/wavedrom

  :ocean: Digital timing diagram rendering engine

  Language:JavaScript2.9k351

• 3b1b/manim

  Animation engine for explanatory math videos

  Language:Python60.6k5.7k