poemonsense

Life is short, work hard

Institute of Computing Technology, CASBeijing

Pinned Repositories

difftest
Modern co-simulation framework for RISC-V CPUs
Language:C++108 4 3562
xfuzz
Fuzzing General-Purpose Hardware Designs with Software Fuzzers
Language:Scala10 8 41
XiangShan
Open-source high-performance RISC-V processor
Language:Scala4.6k 90 374637
chisel
Chisel: A Modern Hardware Design Language
Language:Scala00
chisel-playground
Language:Scala00
circt
Circuit IR Compilers and Tools
Language:C++00
fuzzing-101-solutions
Companion repository to the Fuzzing101 with LibAFL series of blog posts.
Language:C00
micro2022-xs-artifact-evaluation
For artifact evaluation of MICRO-2022
Language:Makefile0 2 00
MultiKeySort
Multi-keyword Sort Project for Data Structure in UCAS
Language:C++0 4 00
rocket-chip
Rocket Chip Generator
Language:Scala10

poemonsense's Repositories

poemonsense/rocket-chip
Rocket Chip Generator
Language:Scala10
poemonsense/chisel
Chisel: A Modern Hardware Design Language
Language:Scala00
poemonsense/chisel-playground
Language:Scala00
poemonsense/circt
Circuit IR Compilers and Tools
Language:C++00
poemonsense/fuzzing-101-solutions
Companion repository to the Fuzzing101 with LibAFL series of blog posts.
Language:C00
poemonsense/micro2022-xs-artifact-evaluation
For artifact evaluation of MICRO-2022
Language:Makefile0 2 00
poemonsense/MultiKeySort
Multi-keyword Sort Project for Data Structure in UCAS
Language:C++0 4 00
poemonsense/nus-cs3211
Projects for CS3211 Parallel and Concurrent Programming, National University of Singapore, AY 2017-18
Language:C0 2 00
poemonsense/rfuzz
rfuzz: coverage-directed fuzzing for RTL research platform
Language:Rust00
poemonsense/riscv-isa-manual
RISC-V Instruction Set Manual
Language:TeX00
poemonsense/riscv-isa-sim
Spike, a RISC-V ISA Simulator
Language:C00
poemonsense/riscv-linux
RISC-V Linux Port
Language:C0 2 00
poemonsense/verilator
Verilator open-source SystemVerilog simulator and lint system
Language:C++00
poemonsense/riscv-pk