poemonsense

poemonsense's Stars

• ccfddl/ccf-deadlines

  ⏰ Collaboratively track deadlines of conferences recommended by CCF (Website, Python Cli, Wechat Applet) / If you find it useful, please star this project, thanks~

  Language:Vue6.7k2291455

• OpenXiangShan/XiangShan

  Open-source high-performance RISC-V processor

  Language:Scala5.4k87436693

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala4.1k1531.1k609

• riscv/riscv-isa-manual

  RISC-V Instruction Set Manual

  Language:TeX3.8k212931653

• rougier/matplotlib-cheatsheet

  Matplotlib 3.1 cheat sheet.

  Language:Python2.9k922401

• XUANTIE-RV/openc910

  OpenXuantie - OpenC910 Core

  Language:Verilog1.2k4629315

• uds-se/fuzzingbook

  Project page for "The Fuzzing Book"

  Language:Jupyter Notebook1.1k42102233

• cryptonomex/graphene

  Language:C++1k159641336

• schoeberl/chisel-book

  Digital Design with Chisel

  Language:TeX7883619144

• THU-DSP-LAB/ventus-gpgpu

  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

  Language:Scala659143277

• riscv-software-src/riscv-pk

  RISC-V Proxy Kernel

  Language:C60158177310

• CMU-SAFARI/ramulator

  A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

  Language:C++6006199210

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  50043548

• OSCC-Project/iEDA

  Language:C++3354934

• yakivmospan/github-wikito-converter

  Generate HTML & PDF documentation from Github wiki or any other markdown-based wiki.

  Language:HTML29844152

• 16bit-ykiko/magic-cpp

  A C++20 header-only library that supports powerful reflection for C++

  Language:C++2703915

• chipsalliance/dromajo

  RISC-V RV64GC emulator designed for RTL co-simulation

  Language:C++219162962

• ucb-bar/constellation

  A Chisel RTL generator for network-on-chip interconnects

  Language:Scala180184427

• Lingrui98/RISC-V-book

  A translation project of the RISC-V reader

  174112043

• chipsalliance/t1

  Language:Scala125123023

• IntelLabs/PreSiFuzz

  Pre-Silicon Hardware Fuzzing Toolkit

  Language:Rust54624

• TeamVoss/VossII

  The source code to the Voss II Hardware Verification Suite

  Language:Verilog5371213

• sifive/riscv-vector-intrinsic-fuzzing

  A random fuzz generator for the RISC-V vector extension intrinsics

  Language:C20686

• chipsalliance/diplomacy

  Language:Scala1822810

• ekiwi/simulator-independent-coverage

  Project Repo for the Simulator Independent Coverage Research

  Language:C++18401

• ljwljwljwljw/DiplomaticBackend

  Language:Scala17100

• bytedance/emuMonitor

  emuMonitor is a tool for "palladium" and "zebu" usage information data-collection, data-analysis and data-display.

  Language:Python9204

• iscas-tis/riscv-spec-core

  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.

  Language:Scala9205

• GeorgeLyon/SwiftHDL

  HDL embedded in Swift powered by CIRCT and MLIR

  Language:C++8200

• parsa-epfl/xsofs

  XiangShan over FireSim

  Language:SystemVerilog7310