Final project of LD(Logic Design) course in Amirkabir University Of Technology.
implemented sequntial and combinational circuit using verilog language. it contain various adder, multiplier, mux and comparator.
The final project of the logic design course is the design of a health care system that receives different vital and individual characteristics from the user and by analyzing and checking them, announces different warnings to the user. The purpose of this project is to familiarize students with the design of a real-time embedded system.
This system evaluates many things using input information.
pouyanhessabi/LD-final-project
Final project of LD(Logic Design) course in Amirkabir University Of Technology.
Verilog