Pinned Repositories
4G-Handover-Optimisation
EE475 project that is to model, simulate and optimise base station handovers in a 4G system
algorithm-exercise
Data Structure and Algorithm notes. 数据结构与算法/leetcode/lintcode题解/
Algorithms
全面的算法代码仓库
architecture_learn
Record what I learn about computer architecture.
Bit_Manipulation_RISC_V
For Bit manipulation analysis, implementation, and documentation within the workgroup.
Documentation_RISC-V
Documentation_Spike
Documentation for RISC-V Spike
opensparc_riscv
porting opensparc t2 to risc-v. Change its front end from sparc to rv64.
practice_leetcode_and_interview
coding practice for my interview about google or other companies. Mainly about leetcode or other practice.
riscv-linux-read
Note for all my understanding of linux on risc-v
poweihuang17's Repositories
poweihuang17/CCiA
:book: C++ Concurrency in Action - Practical Multithreading
poweihuang17/gpgpu-sim_distribution
GPGPU-Sim provides a detailed simulation model of a contemporary GPU (such as NVIDIA's Fermi and GT200 architectures) running CUDA and/or OpenCL workloads and now includes an integrated (and validated) energy model, GPUWattch.
poweihuang17/algorithm
Algorithm Problems I solved... as a hobby
poweihuang17/competitive-programming
my foray into the world of competitive programming
poweihuang17/competitive-programming-book
Data Structures & Algorithms From Competitive Programming Book
poweihuang17/D-Spur
The code for our Robot.
poweihuang17/Discussion_RISC-V
poweihuang17/f32c
A 32-bit RISC-V / MIPS retargetable CPU core
poweihuang17/Open_GPGPU
An open source GPGPU systemverilog project.
poweihuang17/pulpino
An open-source microcontroller system based on RISC-V
poweihuang17/research
dataset and code for 2016 paper "Learning a Driving Simulator"
poweihuang17/ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
poweihuang17/riscv-boom
Berkeley Out-of-Order Machine
poweihuang17/riscv-fesvr
RISC-V Frontend Server
poweihuang17/rocket
Rocket Microarchitectural Implementation of RISC-V ISA
poweihuang17/yarvi
Yet Another RISC-V Implementation