Awesome Open Source EDA Projects
A curated list of EDA open source projects. Please feel free to update this page through submitting pull requests or emailing me.
Table of Contents
Projects (sorted by year)
1999
2002
2004
2005
2009
2010
2011
2012
- PyMTL: Python-based hardware modeling framework
- Yosys Open SYnthesis Suite
- Verilog to Routing -- Open Source CAD Flow for FPGA Research
2013
2014
2015
- OpenTimer: A High-performance Timing Analysis Tool for VLSI Systems
- Ophidian: Open-Source Library for Physical Design Research and Teaching.
- OpenMPL
2016
- A Modeling and Verification Platform for SoCs using ILAs
- Mixed Hardware/Software Emulation
- SystemC TLM Interfaces
- BoxRouter (Global Router)
2017
2018
- Lgraph: Live Graph infrastructure for Synthesis and Simulation
- OpenPiton
- Cpp-Taskflow
- Parser-SPEF
- DATCRobustDesignFlow
- EPFLLogicSynthesisLibraries
- OpenSTA
- RePlace
- TritoCTS
- TritonSizer
- BSD-DME
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
- LeWiz Communications, Inc. Ethernet MAC Core1 - Ethernet 1G/100M/10M
- 12nm RAIL library
- 65nm RAIL Library
- A framework for FPGA emulation of mixed-signal systems
- AXI Protocol Checker
- CoreIR Symbolic Analyzer
- Open-source FPGA Workflow
- FPGA-SPICE
- Tools regarding on analog modeling, validation, and generation
- OpenDP (Open Source Detailed Placement)
- University of Minnesota / Intel (Automated Analog Layout)
- gds2Para (Complete Integrated Circuit (IC) Layout Analysis from GDSII Design File to Parasitics Extraction)
- University of Utah (Logic Synthesis)
- JITX (Intent Driven Board Design)
- The EPFL Combinational Benchmark Suite
2019
- Analog Known Good Designs
- Analog Parameter Search Engine
- Brown (Open Source PVT Sensors)
- Circuit IP Sanitizer
- Serial Link Mixed Signal Modeling
- UW-IDEA_AnalogTestCases
- System Verilog to Verilog
- Asynchronous Memory Compiler
- University of Michigan (Intent Driven Analog Design)
- Machine Generated Analog IC Layout
- Magical Test Circuits
- UW BSG Pipecleaner Suite
- OpenPiton Design Benchmark
- System Verilog to Verilog
- Utd-SystemVerilog
Summary
Year | Number | Cumulative Number |
---|---|---|
1999 | 1 | 1 |
2002 | 1 | 2 |
2004 | 1 | 3 |
2005 | 1 | 4 |
2009 | 1 | 5 |
2010 | 1 | 6 |
2011 | 1 | 7 |
2012 | 3 | 10 |
2013 | 1 | 11 |
2014 | 2 | 13 |
2015 | 3 | 16 |
2016 | 4 | 20 |
2017 | 5 | 25 |
2018 | 28 | 53 |
2019 | 15 | 68 |
Reference
- T.-W. Huang, C.-X. Lin, G. Guo, and Martin D. F. Wong, Essential Building Blocks for Creating an Open-source EDA Project, ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, 2019.
- Essential Building Blocks for Creating an Open-source EDA Project. Invited talk at DAC.
- DARPA Intelligent Design of Electronic Assets (IDEA)
- DARPA Posh Open Source Hardware (POSH)
- List of IDEA Projects
- List of POSH Projects