/hslink_phy

Verilog functional model for PHY

Primary LanguagePythonBSD 3-Clause "New" or "Revised" LicenseBSD-3-Clause

Open Source PHY Architecture

Introduction

This repository contains an ADC-based high-speed link design, along with the behavioral models and simulation framework needed to test it. Certain parts of the design are parameterized (such as the number of filter taps), and it's possible to simulate the link behavior for an arbitrary channel by providing a file of S-parameters.

Running the demo

  1. First set up the shell environment:
> source setup.cshrc
  1. Then go into the channel/model folder:
> cd channel/model
  1. Build the channel models:
> make
  1. Next, go into the architect/sim folder:
> cd ../../architect/sim
  1. Run the simulation:
> make
  1. View the simulation waveforms with SimVision.
> simvision

Sample results as viewed in SimVision