Upscale

Pinned Repositories

aqed-dac2020-results
Source files to reproduce the results shown for A-QED at DAC 2020
Language:C++7 3 33
aqed-decomp-FMCAD2021
Experiments related to our FMCAD 2021 paper "Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition"
Language:C5 2 10
case-studies
Case studies
Language:Verilog5 2 22
cosa2
Next generation CoSA.
Language:C++3 3 00
eqed-artifact
Language:Python1 3 20
generic-sqed-demo
Language:Verilog10 3 13
hslink_phy
Verilog functional model for PHY
Language:Python7 4 16
ridecore-si-checking
Single instruction checking for RIDECORE
Language:Verilog3 5 01
sqed-generator
Python-based workflow to generate QED modules from ISA/architecture specifications
Language:Verilog2 3 53

Upscale's Repositories

upscale-project/generic-sqed-demo
Language:Verilog10 3 13
upscale-project/aqed-dac2020-results
Source files to reproduce the results shown for A-QED at DAC 2020
Language:C++7 3 33
upscale-project/hslink_phy
Verilog functional model for PHY
Language:Python7 4 16
upscale-project/aqed-decomp-FMCAD2021
Experiments related to our FMCAD 2021 paper "Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition"
Language:C5 2 10
upscale-project/case-studies
Case studies
Language:Verilog5 2 22
upscale-project/cosa2
Next generation CoSA.
Language:C++3 3 00
upscale-project/ridecore-si-checking
Single instruction checking for RIDECORE
Language:Verilog3 5 01
upscale-project/sqed-generator
Python-based workflow to generate QED modules from ISA/architecture specifications
Language:Verilog2 3 53
upscale-project/eqed-artifact
Language:Python1 3 20