Memory Layout

[noahzarro]

According to the RISC-V CLIC spec, the memory layout of the memory mapped registers should be as follows:

  0x1000+4*i 1B/input R or RW clicintip[i]
  0x1001+4*i 1B/input RW clicintie[i]
  0x1002+4*i 1B/input RW clicintattr[i]
  0x1003+4*i 1B/input RW clicintctl[i]
  ...
  0x4FFC 1B/input R or RW clicintip[4095]
  0x4FFD 1B/input RW clicintie[4095]
  0x4FFE 1B/input RW clicintattr[4095]
  0x4FFF 1B/input RW clicintctl[4095]

The clicint[ip/ie/attr/clt] registers have a width of 1 byte. See https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc#clic-memory-map

However, in the current implementation they are 4 bytes wide.