missing assertions.svh in common_cells.core

[qian-gu]

Thanks for this great job, but I have get an error message when re-using some module with the fusesoc tool in a simple test project. Partial content of my core file is as bellow:

filesets:
  rtl:
    depend:
      - ">=pulp-platform.org::common_cells:1.26.0"
    files:
      - rtl/blinky_pkg.sv
      - rtl/blinky.sv
      - rtl/step_counter.sv
    file_type: systemVerilogSource

What I want is only the delta_counter module while as the whole library is added to my project, fusesoc can't find the assertions.svh file for stream_fifo_optimal_wrap module when run lint or simulation with verilator. The problem is resovled by adding the header file in the common_cells.core file as bellow:

CAPI=2:

name : pulp-platform.org::common_cells:1.26.0

filesets:
  rtl:
    files:
      - include/common_cells/registers.svh : {is_include_file : true, include_path : include}
      - include/common_cells/assertions.svh : {is_include_file : true, include_path : include}
      # Source files grouped in levels. Files in level 0 have no dependencies on files in this package.
      # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0,
      # etc. Files within a level are ordered alphabetically.
      - src/binary_to_gray.sv
      # ...

My question is :

1. whether the assertions.svh is excluded intentionally or not ?
2. and if the answer is yes, how to avoid this problem in other designs excepting modify the common_cells.core file locally ?

[niwis]

Hi! I'm not aware of any reasons why assertions.svh should be excluded. It looks like the recently added stream_fifo_optimal_wrap module is the first common-cells module to use this file, which is why it wasn't needed before.

Feel free to open a PR to add this!