Pinned Repositories
AXI4Test
Chisel3 AXI4 memory mapped register
caravel_asic_one
caravel_user_project
https://caravel-user-project.readthedocs.io
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
computer-engineering-resources
A curated list of Computer Engineering resources
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cve2
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
dsp-blocks
A collection of common Digital Signal Processing block generators
pznikola's Repositories
pznikola/AXI4Test
Chisel3 AXI4 memory mapped register
pznikola/caravel_asic_one
pznikola/caravel_user_project
https://caravel-user-project.readthedocs.io
pznikola/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
pznikola/computer-engineering-resources
A curated list of Computer Engineering resources
pznikola/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
pznikola/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
pznikola/cve2
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
pznikola/cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
pznikola/dsp-blocks
A collection of common Digital Signal Processing block generators
pznikola/ethernet-wrapper
Chisel wrapper for Alex Forencich ethernet.
pznikola/fastvdma
Antmicro's fast, vendor-neutral DMA IP in Chisel
pznikola/fpga-shells
pznikola/InterpolatorAndFIRs
ETF students project - Digital signal Interpolation
pznikola/QueueCIRCT
pznikola/rocket-chip
Rocket Chip Generator
pznikola/rocket-chip-fpga-shells
Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
pznikola/SystemVerilog_student_exercises
Simple exercises in SystemVerilog for students
pznikola/testchipip
pznikola/verilog-ethernet
Verilog Ethernet components for FPGA implementation
pznikola/XiangShan
Open-source high-performance RISC-V processor