pznikola

pznikola's Stars

• rougier/scientific-visualization-book

  An open access book on scientific visualization using python and matplotlib

  Language:Python10.8k19043995

• hneemann/Digital

  A digital logic designer and circuit simulator.

  Language:Java4.6k92944473

• lincolnloop/python-qrcode

  Python QR Code image generator

  Language:Python4.5k122250693

• XUANTIE-RV/wujian100_open

  IC design and development should be faster，simpler and more reliable

  Language:Verilog1.9k14046575

• gem5/gem5

  The official repository for the gem5 computer-system architecture simulator.

  Language:C++1.8k703721.3k

• riscv-mcu/e203_hbirdv2

  The Ultra-Low Power RISC-V Core

  Language:Verilog1.4k3721352

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.2k40123275

• riscvarchive/riscv-cores-list

  RISC-V Cores, SoC platforms and SoCs

  859584209

• AnMnv/eBook

  LaTeX book with examples, open-source eBook

  Language:TeX5439221

• aolofsson/awesome-semiconductor-startups

  List of awesome semiconductor startups

  Language:Python5343610482

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  51443551

• open-logic/open-logic

  Open Logic FPGA Standard Library

  Language:VHDL472223042

• adki/AMBA_AXI_AHB_APB

  AMBA bus lecture material

  Language:Verilog40490130

• chipsalliance/sv-tests

  Test suite designed to check compliance with the SystemVerilog standard.

  Language:SystemVerilog3061928075

• AngeloJacobo/UberDDR3

  Opensource DDR3 Controller

  Language:Verilog2599939

• Evensgn/RISC-V-CPU

  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

  Language:Verilog2503141

• HewlettPackard/mcpat

  An integrated power, area, and timing modeling framework for multicore and manycore architectures

  Language:C++17810569

• cpc/openasip

  Open Application-Specific Instruction Set processor tools (OpenASIP)

  Language:C1531512345

• ucsc-vama/essent

  high-performance RTL simulator

  Language:Scala1519813

• openhwgroup/cv32e40s

  4 stage, in-order, secure RISC-V core based on the CV32E40P

  Language:SystemVerilog140179224

• dian-lun-lin/RTLflow

  A GPU acceleration flow for RTL simulation with batch stimulus

  Language:C++102607

• edaplayground/eda-playground

  EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL

  Language:HTML5856717

• SeoLabCornell/torch2chip

  Torch2Chip (MLSys, 2024)

  Language:Python51145

• samerps/Blender-FastHenry

  Blender FastHenry - FastHenry simulations in Blender

  Language:Python483312

• bsc-loca/sauria

  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

  Language:SystemVerilog27208

• broccolimicro/loom

  design and verification of asynchronous circuits

  Language:Python173270

• artecs-group/RVfpga-sim-addons

  Recent updates and features added to the RVfpga course developed by Imagination Technologies.

  Language:C14403

• broccolimicro/floret

  Automated custom cell layout generator

  Language:Python8110

• lewiz-support/LVDS_Transceiver

  4101

• fpganinja/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog3000