qcjiang

22digital

22digital problem for ai course

bhive

Reimplementation of the BHive profiler. The original can be found here: https://github.com/ithemal/bhive.

compiler

大三上编译原理课程实验-PL/0编译器的设计与扩展

DAMOV

DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is intended to study new architectures, such as near-data processing. Described by Oliveira et al. (preliminary version at https://arxiv.org/pdf/2105.03725.pdf)

Enhanced-Bhive

This repository is an improved version of Bhive (https://github.com/ithemal/bhive). The original Bhive version utilized system calls to read PMU counters and generate results, resulting in approximately 300 cycles of BIAS. In this version, we utilized REIGSTER MOVEMENT to perform the same operations, which can effectively remove the BIAS.

gem5

gem5 dev version for ramulator

HSCC

HSCC is implemented with zsim-nvmain hybrid simulator, it has achieved the following functions: (1) Memory management simulations (such as MemoryNode, Zone, Buddy Allocator etc.); (2) TLB, page table and reversed page table simulations; (3) Implementation of SHMA, a hierarchical hybrid DRAM/NVM memory system that brought DRAM caching issues into so

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

sudoku_solver

基于回溯法的GUI解数独工具

OSACA

Open Source Architecture Code Analyzer

qcjiang/compiler

大三上编译原理课程实验-PL/0编译器的设计与扩展

qcjiang/Enhanced-Bhive

This repository is an improved version of Bhive (https://github.com/ithemal/bhive). The original Bhive version utilized system calls to read PMU counters and generate results, resulting in approximately 300 cycles of BIAS. In this version, we utilized REIGSTER MOVEMENT to perform the same operations, which can effectively remove the BIAS.

qcjiang/DAMOV

DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is intended to study new architectures, such as near-data processing. Described by Oliveira et al. (preliminary version at https://arxiv.org/pdf/2105.03725.pdf)

qcjiang/HSCC

HSCC is implemented with zsim-nvmain hybrid simulator, it has achieved the following functions: (1) Memory management simulations (such as MemoryNode, Zone, Buddy Allocator etc.); (2) TLB, page table and reversed page table simulations; (3) Implementation of SHMA, a hierarchical hybrid DRAM/NVM memory system that brought DRAM caching issues into so

qcjiang/sudoku_solver

基于回溯法的GUI解数独工具

qcjiang/22digital

22digital problem for ai course

qcjiang/bhive

Reimplementation of the BHive profiler. The original can be found here: https://github.com/ithemal/bhive.

qcjiang/calculator

GUI calculator base on wxpython

qcjiang/COD-lab

组成原理课程实验以及最后大作业

qcjiang/gem5

gem5 dev version for ramulator

qcjiang/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

qcjiang/graphBIG

A Comprehensive Benchmark Suite for Graph Computing for validating VIRTUOSO (https://github.com/CMU-SAFARI/Virtuoso)

qcjiang/ibench

Measure instruction latency and throughput

qcjiang/Introduction-to-Algorithms

大三上算法导论课程实验

qcjiang/mcpat

An integrated power, area, and timing modeling framework for multicore and manycore architectures

qcjiang/Mobile-PIM

qcjiang/mp3_player

基于Spartan-3E 开发板与一个无源蜂鸣器的mp3播放器 可播放科大校歌

qcjiang/Operating-System

操作系统实验

qcjiang/OSACA

Open Source Architecture Code Analyzer

qcjiang/pku-oj

百练习题集

qcjiang/pmevo-artifact

PLDI'20 Research Artifact for the PMEvo Project

qcjiang/qcjiang.github.io

My homepage

qcjiang/ramulator-pim

A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL

qcjiang/RawHash

RawHash is the first mechanism that can accurately and efficiently map raw nanopore signals to large reference genomes (e.g., a human reference genome) in real-time without using powerful computational resources (e.g., GPUs). Described by Firtina et al. (published at https://academic.oup.com/bioinformatics/article/39/Supplement_1/i297/7210440)

qcjiang/storm-optimization-reports

USTC Team repo for 7th RDMA Programming Competition held by HPC Advisory Council

qcjiang/vim-conf

My vim configurations.

qcjiang/Virtuoso

Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.