Run: Synthesis Implementation (and bitstream) Generation
NOTE: Board files for the given FPGA device should already be installed and the FPGA device should be connected prior to starting this script
Modify the last parameter in each statement.
Example: set {project_name} risc_v_cpu
set {project_name} *project_name*
Example: set {project_path} /home/user/fpga/
set {project_path} *absolute_path_of_the_files*
NOTE: First line should contain the top file
Example: set hdl_source_code(0) top
set hdl_source_code(0) *verilog_file_1*
set hdl_source_code(1) *verilog_file_2*
set hdl_source_code(2) *verilog_file_3*
Example: set {constraint} zybo-z710
set {constraint} *constraint*
Example: For Digilent Zybo-Z7-10
set {fpga_part} xc7z010clg400-1
set {fpga_id} xc7z010_1
set {fpga_board} digilentinc.com:zybo-z7-10:part0:1.0
set {fpga_part} *fpga_part*
set {fpga_id} *fpga_id*
set {fpga_board} *board_information*
a. Place this script along with all the Verilog files
b. Start Xilinx Vivado
c. Change directory to the location of current files
d. Finally, start the script with
source rsig.tcl
TODO: Automate the process of file addition.
TODO: Automate the device add process.
This script was tested in Xilinx Vivado 2020.2 running on Ubuntu 20.04.