reedv/Simple-MIPS-CPU
A simple pipelined MIPS CPU implemented in verilog. Can perform add, addi, beq, j, lw, and sw instructions.
Verilog
No issues in this repository yet.
A simple pipelined MIPS CPU implemented in verilog. Can perform add, addi, beq, j, lw, and sw instructions.
Verilog
No issues in this repository yet.