rherveille

Pinned Repositories

• synlig

  SystemVerilog support for Yosys

  Language:Verilog1581623921

• adv_dbg_if

  Universal Advanced JTAG Debug Interface

  Language:SystemVerilog175111

• ahb3lite_apb_bridge

  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

  Language:SystemVerilog405319

• ahb3lite_interconnect

  AHB3-Lite Interconnect

  Language:SystemVerilog819427

• ahb3lite_memory

  Multi-Technology RAM with AHB3Lite interface

  Language:SystemVerilog195216

• ahb3lite_pkg

  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces

  Language:SystemVerilog157010

• Hamming-ECC

  Hamming ECC Encoder and Decoder to protect memories

  Language:SystemVerilog264222

• plic

  Platform Level Interrupt Controller

  Language:SystemVerilog346814

• RV12

  RISC-V CPU Core

  Language:SystemVerilog282201550

• yosys

  Yosys Open SYnthesis Suite

  Language:C++3.4k1381.7k871

rherveille's Repositories