risclite

ARM9-compatible-soft-CPU-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

R8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

risclite.github.io

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

rv32m-multiplier-and-divider

a multiplier&divider verilog RTL file for RV32M instructions

rv3n

RV3N--- a RV32IMC processor core, which has a new pipeline with "3+N" stages.

SuperScalar-RISCV-CPU

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

verilog-divider

a super-simple pipelined verilog divider. flexible to define stages

risclite/SuperScalar-RISCV-CPU

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

risclite/R8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

risclite/ARM9-compatible-soft-CPU-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

risclite/verilog-divider

a super-simple pipelined verilog divider. flexible to define stages

risclite/rv32m-multiplier-and-divider

a multiplier&divider verilog RTL file for RV32M instructions

risclite/rv3n

RV3N--- a RV32IMC processor core, which has a new pipeline with "3+N" stages.

risclite/riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

risclite/risclite.github.io