Using new toolchain (12.2) csr opcode errors.
Opened this issue · 5 comments
InspireSemi commented
The _zicsr and _zifecei options for -march are no longer assumed if you specify i as an option to -march=
For test cases that have any csr opcodes in them 9DUT or Sail) it will fail the compile with a message:
Error: unrecognized opcode csrr a0,mhartid', extension zicsr' required
Currently the python scripts for generating makefile for both the DUT and Sail use as passed in parameter {0}
-march={0} which for testing C extension translates to -march=rv64ic
Changing the python to a fixed value of : -march=rv64imafdc_zicsr_zifencei instead of the {0} fixes this issue and allows the test cases to compile w/o errors.
I do not know if this is the long term fix for this as some cross-compilers may not support the full extension set, based on how they were built.
Abdulwadoodd commented
Each test file has the RVTEST_ISA function that defines the ISA string which is picked up by the RISCOF and passed to -march flag.
And each test has an appropriate ISA string depending on the Instruction OPCODES that the test executes. For example for the C extension tests, the RVTEST_ISA is defined as RV64IC (which translates to -march=rv64ic), except for c.ebreak test. As c.ebreak raises an exception, it executes CSR opcodes. Hence, zicsr is included in the ISA string for this test (link).
So, the test carefully includes only those minimum extensions/features to the ISA string that are required by the test. Since the C extension tests do not execute (or are not required to execute) CSR opcodes (except c.ebreak), so ISA string only includes ic and does not include zicsr. If there is a bug in the implementation (or the C extension is disabled in the implementation), it may cause a trap and tries to execute CSR opcodes, then the toolchain will throw the compilation error because zicsr is not included (and not required to be included by that test)
InspireSemi commented
The problem comes in when a DUT/Sail uses csr in its model code. This will cause the test to fail, actually crashes the whole test..
The test cannot just assume because the test case does not use extension X it is not used in the model files for either the DUT or Sail.
What is the downside to hardcoding a value for this as opposed to basing this on the test case being run? Or defining this in the DUT yaml file to then be used in the python file?
I think we need to discuss this at the next committee meeting.
Marc Karasek
Principal Software Engineer
M: 678.770.3788
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From: Wadood ***@***.***>
Sent: Friday, June 2, 2023 11:21 AM
To: riscv-non-isa/riscv-arch-test ***@***.***>
Cc: Marc Karasek ***@***.***>; Author ***@***.***>
Subject: Re: [riscv-non-isa/riscv-arch-test] Using new toolchain (12.2) csr opcode errors. (Issue #359)
Each test file has the RVTEST_ISA function that defines the ISA string which is picked up by the RISCOF and passed to -march flag.
And each test has an appropriate ISA string depending on the Instruction OPCODES that the test executes. For example for the C extension tests, the RVTEST_ISA is defined as RV64IC<https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv64i_m/C/src/cxor-01.S%23L20___.YXAzOmluc3BpcmVzZW1pOmE6bzpmYTBmNDc0MWUxYjA2OGQ2YWFiNDQ3NmM1YWNlYmIwNjo2OjNlZDA6NWJjMzQzMDRmYjFlNjA1MzZjYjM3ZThlOWVjYWExODdmMWU5ZDQxY2U4MzVkYzM1NmQ3MDJkZTlkNjFhNmQzZTpoOlQ> (which translates to -march=rv64ic), except for c.ebreak test. As c.ebreak raises an exception, it executes CSR opcodes. Hence, zicsr is included in the ISA string for this test (link<https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-ar%20ch-test/blob/main/riscv-test-suite/rv64i_m/C/src/cebreak-01.S___.YXAzOmluc3BpcmVzZW1pOmE6bzpmYTBmNDc0MWUxYjA2OGQ2YWFiNDQ3NmM1YWNlYmIwNjo2OmFhZTU6Njg2ZTljOTE5YTNlMmUyOWE4MmY2MzEyNzhiYWRlNjAxNTMxNmQzODlkYTczYzlmNTA1MDA1ZDAzYThjN2M2MzpoOlQ>).
So, the test carefully includes only those minimum extensions/features to the ISA string that are required by the test. Since the C extension tests do not execute (or are not required to execute) CSR opcodes (except c.ebreak), so ISA string only includes ic and does not include zicsr. If there is a bug in the implementation (or the C extension is disabled in the implementation), it may cause a trap and tries to execute CSR opcodes, then the toolchain will throw the compilation error because zicsr is not included (and not required to be included by that test)
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InspireSemi commented
Example from our DUT that uses csr opcodes in test case:
//RVMODEL_BOOT
#define RVMODEL_BOOT \
.section .text.init; \
.extern _fsignature; \
csrr a0, mhartid ;\
li a1, 0x00 ;\
beq a1, a0, cont ;\
55: \
wfi ;\
j 55b ;\
cont: ;\
RVMODEL_IO_INIT;
This allows only 1 hart to proceed to runt he tests and puts any other hart into a wfi state.
Marc Karasek
Principal Software Engineer
M: 678.770.3788
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From: Wadood ***@***.***>
Sent: Friday, June 2, 2023 11:21 AM
To: riscv-non-isa/riscv-arch-test ***@***.***>
Cc: Marc Karasek ***@***.***>; Author ***@***.***>
Subject: Re: [riscv-non-isa/riscv-arch-test] Using new toolchain (12.2) csr opcode errors. (Issue #359)
Each test file has the RVTEST_ISA function that defines the ISA string which is picked up by the RISCOF and passed to -march flag.
And each test has an appropriate ISA string depending on the Instruction OPCODES that the test executes. For example for the C extension tests, the RVTEST_ISA is defined as RV64IC<https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv64i_m/C/src/cxor-01.S%23L20___.YXAzOmluc3BpcmVzZW1pOmE6bzpmYTBmNDc0MWUxYjA2OGQ2YWFiNDQ3NmM1YWNlYmIwNjo2OjNlZDA6NWJjMzQzMDRmYjFlNjA1MzZjYjM3ZThlOWVjYWExODdmMWU5ZDQxY2U4MzVkYzM1NmQ3MDJkZTlkNjFhNmQzZTpoOlQ> (which translates to -march=rv64ic), except for c.ebreak test. As c.ebreak raises an exception, it executes CSR opcodes. Hence, zicsr is included in the ISA string for this test (link<https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-ar%20ch-test/blob/main/riscv-test-suite/rv64i_m/C/src/cebreak-01.S___.YXAzOmluc3BpcmVzZW1pOmE6bzpmYTBmNDc0MWUxYjA2OGQ2YWFiNDQ3NmM1YWNlYmIwNjo2OmFhZTU6Njg2ZTljOTE5YTNlMmUyOWE4MmY2MzEyNzhiYWRlNjAxNTMxNmQzODlkYTczYzlmNTA1MDA1ZDAzYThjN2M2MzpoOlQ>).
So, the test carefully includes only those minimum extensions/features to the ISA string that are required by the test. Since the C extension tests do not execute (or are not required to execute) CSR opcodes (except c.ebreak), so ISA string only includes ic and does not include zicsr. If there is a bug in the implementation (or the C extension is disabled in the implementation), it may cause a trap and tries to execute CSR opcodes, then the toolchain will throw the compilation error because zicsr is not included (and not required to be included by that test)
—
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allenjbaum commented
I think the short description is:
- you have provided a string (or the riscv-config YAML) that says you
support Zicsr,
- you require Zicsr in your boot code,
- but if the test doesn't require Zicsr, it tries to compile the test (and
your boot code) without that string
and therefore the compile fails?
…On Fri, Jun 2, 2023 at 9:55 AM InspireSemi ***@***.***> wrote:
Example from our DUT that uses csr opcodes in test case:
//RVMODEL_BOOT
#define RVMODEL_BOOT \
.section .text.init; \
.extern _fsignature; \
csrr a0, mhartid ;\
li a1, 0x00 ;\
beq a1, a0, cont ;\
55: \
wfi ;\
j 55b ;\
cont: ;\
RVMODEL_IO_INIT;
This allows only 1 hart to proceed to runt he tests and puts any other
hart into a wfi state.
Marc Karasek
Principal Software Engineer
M: 678.770.3788
[A close up of a sign Description automatically generated]
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WHICH IT IS ADDRESSED AND MAY CONTAIN INFORMATION THAT IS PRIVILEGED,
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From: Wadood ***@***.***>
Sent: Friday, June 2, 2023 11:21 AM
To: riscv-non-isa/riscv-arch-test ***@***.***>
Cc: Marc Karasek ***@***.***>; Author ***@***.***>
Subject: Re: [riscv-non-isa/riscv-arch-test] Using new toolchain (12.2)
csr opcode errors. (Issue #359)
Each test file has the RVTEST_ISA function that defines the ISA string
which is picked up by the RISCOF and passed to -march flag.
And each test has an appropriate ISA string depending on the Instruction
OPCODES that the test executes. For example for the C extension tests, the
RVTEST_ISA is defined as RV64IC<
https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv64i_m/C/src/cxor-01.S%23L20___.YXAzOmluc3BpcmVzZW1pOmE6bzpmYTBmNDc0MWUxYjA2OGQ2YWFiNDQ3NmM1YWNlYmIwNjo2OjNlZDA6NWJjMzQzMDRmYjFlNjA1MzZjYjM3ZThlOWVjYWExODdmMWU5ZDQxY2U4MzVkYzM1NmQ3MDJkZTlkNjFhNmQzZTpoOlQ>
(which translates to -march=rv64ic), except for c.ebreak test. As c.ebreak
raises an exception, it executes CSR opcodes. Hence, zicsr is included in
the ISA string for this test (link<
https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-ar%20ch-test/blob/main/riscv-test-suite/rv64i_m/C/src/cebreak-01.S___.YXAzOmluc3BpcmVzZW1pOmE6bzpmYTBmNDc0MWUxYjA2OGQ2YWFiNDQ3NmM1YWNlYmIwNjo2OmFhZTU6Njg2ZTljOTE5YTNlMmUyOWE4MmY2MzEyNzhiYWRlNjAxNTMxNmQzODlkYTczYzlmNTA1MDA1ZDAzYThjN2M2MzpoOlQ>).
So, the test carefully includes only those minimum extensions/features to
the ISA string that are required by the test. Since the C extension tests
do not execute (or are not required to execute) CSR opcodes (except
c.ebreak), so ISA string only includes ic and does not include zicsr. If
there is a bug in the implementation (or the C extension is disabled in the
implementation), it may cause a trap and tries to execute CSR opcodes, then
the toolchain will throw the compilation error because zicsr is not
included (and not required to be included by that test)
—
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MarcKarasek commented
Yes
…On Sat, Jun 3, 2023, 3:05 AM Allen Baum ***@***.***> wrote:
I think the short description is:
- you have provided a string (or the riscv-config YAML) that says you
support Zicsr,
- you require Zicsr in your boot code,
- but if the test doesn't require Zicsr, it tries to compile the test (and
your boot code) without that string
and therefore the compile fails?
On Fri, Jun 2, 2023 at 9:55 AM InspireSemi ***@***.***> wrote:
> Example from our DUT that uses csr opcodes in test case:
>
> //RVMODEL_BOOT
> #define RVMODEL_BOOT \
> .section .text.init; \
> .extern _fsignature; \
> csrr a0, mhartid ;\
> li a1, 0x00 ;\
> beq a1, a0, cont ;\
> 55: \
> wfi ;\
> j 55b ;\
> cont: ;\
> RVMODEL_IO_INIT;
>
> This allows only 1 hart to proceed to runt he tests and puts any other
> hart into a wfi state.
>
>
> Marc Karasek
> Principal Software Engineer
> M: 678.770.3788
>
> [A close up of a sign Description automatically generated]
> www.inspiresemi.com<http://www.cryptocoretech.com/>
>
> THIS MESSAGE IS INTENDED ONLY FOR THE USE OF THE INDIVIDUAL OR ENTITY TO
> WHICH IT IS ADDRESSED AND MAY CONTAIN INFORMATION THAT IS PRIVILEGED,
> CONFIDENTIAL AND/OR EXEMPT FROM DISCLOSURE UNDER APPLICABLE LAW. If the
> reader of this message is not the intended recipient or agent responsible
> for delivering the message to the intended recipient, then you are hereby
> notified that any dissemination or copying of this communication is
> strictly prohibited. If you have received this electronic transmission in
> error, please delete it from your system without copying it and notify
the
> sender by reply e-mail so that our address record can be corrected. Thank
> you.
>
> From: Wadood ***@***.***>
> Sent: Friday, June 2, 2023 11:21 AM
> To: riscv-non-isa/riscv-arch-test ***@***.***>
> Cc: Marc Karasek ***@***.***>; Author ***@***.***>
> Subject: Re: [riscv-non-isa/riscv-arch-test] Using new toolchain (12.2)
> csr opcode errors. (Issue #359)
>
>
> Each test file has the RVTEST_ISA function that defines the ISA string
> which is picked up by the RISCOF and passed to -march flag.
> And each test has an appropriate ISA string depending on the Instruction
> OPCODES that the test executes. For example for the C extension tests,
the
> RVTEST_ISA is defined as RV64IC<
>
https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv64i_m/C/src/cxor-01.S%23L20___.YXAzOmluc3BpcmVzZW1pOmE6bzpmYTBmNDc0MWUxYjA2OGQ2YWFiNDQ3NmM1YWNlYmIwNjo2OjNlZDA6NWJjMzQzMDRmYjFlNjA1MzZjYjM3ZThlOWVjYWExODdmMWU5ZDQxY2U4MzVkYzM1NmQ3MDJkZTlkNjFhNmQzZTpoOlQ
>
> (which translates to -march=rv64ic), except for c.ebreak test. As
c.ebreak
> raises an exception, it executes CSR opcodes. Hence, zicsr is included in
> the ISA string for this test (link<
>
https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-ar%20ch-test/blob/main/riscv-test-suite/rv64i_m/C/src/cebreak-01.S___.YXAzOmluc3BpcmVzZW1pOmE6bzpmYTBmNDc0MWUxYjA2OGQ2YWFiNDQ3NmM1YWNlYmIwNjo2OmFhZTU6Njg2ZTljOTE5YTNlMmUyOWE4MmY2MzEyNzhiYWRlNjAxNTMxNmQzODlkYTczYzlmNTA1MDA1ZDAzYThjN2M2MzpoOlQ
>).
>
>
> So, the test carefully includes only those minimum extensions/features to
> the ISA string that are required by the test. Since the C extension tests
> do not execute (or are not required to execute) CSR opcodes (except
> c.ebreak), so ISA string only includes ic and does not include zicsr. If
> there is a bug in the implementation (or the C extension is disabled in
the
> implementation), it may cause a trap and tries to execute CSR opcodes,
then
> the toolchain will throw the compilation error because zicsr is not
> included (and not required to be included by that test)
>
> —
> Reply to this email directly, view it on GitHub<
>
https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-arch-test/issues/359%23issuecomment-1573910157___.YXAzOmluc3BpcmVzZW1pOmE6bzpmYTBmNDc0MWUxYjA2OGQ2YWFiNDQ3NmM1YWNlYmIwNjo2OjkzMjI6ODllZWMwMTA5YjU2NDgwMzBmNWU4NWIxODc4MDY2ZDA2OGEyYTI4ZTY3M2M3ODIyODc4YmNiYWQzMDliM2Q5MjpoOlQ
>,
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