Abdulwadoodd

asynchronous-fifo

The asynchronous FIFO design to transfer parameterized data width from one clock domain to another clock domain.

blinky

Example LED blinking project for your FPGA dev board of choice

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Cores-SweRVolf

FuseSoC-based SoC for SweRV EH1

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

LumosRV

Implementation of 5-stage pipelined RISC-V processor - RV32I - in Verilog

nucleusrv

NucleusRV - A 32-bit 5 staged pipelined risc-v core.

pcie-crd

State Machine of Current Running Disparity calculator for PCI express physical layer

Abdulwadoodd/riscv-arch-test

Abdulwadoodd/asynchronous-fifo

The asynchronous FIFO design to transfer parameterized data width from one clock domain to another clock domain.

Abdulwadoodd/blinky

Example LED blinking project for your FPGA dev board of choice

Abdulwadoodd/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Abdulwadoodd/cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Abdulwadoodd/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Abdulwadoodd/Cores-SweRVolf

FuseSoC-based SoC for SweRV EH1

Abdulwadoodd/ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Abdulwadoodd/LumosRV

Implementation of 5-stage pipelined RISC-V processor - RV32I - in Verilog

Abdulwadoodd/nucleusrv

NucleusRV - A 32-bit 5 staged pipelined risc-v core.

Abdulwadoodd/pcie-crd

State Machine of Current Running Disparity calculator for PCI express physical layer

Abdulwadoodd/riscof

Abdulwadoodd/RISCV-Assembly

RISC-V Assembly Programming for Unprivileged architecture from ground up using Ripes GUI Simulator, Qemu Emulator and Gnu DeBugger (GDB)

Abdulwadoodd/riscv-config

RISC-V Configuration Validator

Abdulwadoodd/riscv-ctg

Abdulwadoodd/riscv-disasm

Open source RISC-V dis-assembler written in C++

Abdulwadoodd/riscv-isa-manual

RISC-V Instruction Set Manual

Abdulwadoodd/rocket-chip

Rocket Chip Generator

Abdulwadoodd/rvv-intrinsic-doc

Abdulwadoodd/sail-riscv

Sail RISC-V model

Abdulwadoodd/serv

SERV - The SErial RISC-V CPU