HOWTO: discover base address of the bank of error registers
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What is the mechanism used to determine the base address of the bank of registers?
Will a CSR be defined? Is it a SW-only managed address?
Context for this question: if I were to implement RERI functionality in the Sail model,
where would I get the address information so I can configure the Sail model?
No CSR will be defined. The base address discovery for the bank of registers should follow the unified discovery mechanism. There may not be a single base address in the system and the error banks implemented by the system do not need to be contiguous in address space. Discovering of base addresses for these registers should follow as done for other non-ISA registers such as those of a PLIC/APLIC, IMSIC, etc.
No hardware as Ved said. This is part of the general discovery issue for ALL memory-mapped components in a system. (Note, for RISC-V Unified Discovery there IS a CSR in Priv 1.12 that points to the UD discovery structure that contains all the discovery info. All the rest of UD is software standardization.)