SID_070: SoC-integrated PCIe devices MAY support programmable BAR registers.
andreiw opened this issue · 3 comments
If I understand correctly, this is a BAR that ignores any writes ("fixed in position"). Similar to what was seen on Pass 1 Cavium ThunderX CN88xx devices, and I recall this being non-standard (it was replaced with fixed EAs in shipping Si). Presumably such systems would also have strange switches (wrt their aperture behavior).
Is there a particular benefit to allowing this behavior? It will mean an OS has to be able to tolerate such behavior (and work around it from the perspective of supporting full resource reconfiguration).
This requirement relates to standard PCIe BARs and not "fixed in position". The PCIe specification does not allow for "fixed in position" BARs. WIll update the text to make it more explicit to state "The BAR registers supported by SoC integrated devices MUST be programmable. When BAR registers are supported, the Memory Space Indicator (bit 0) of such BAR MUST be 1 and they SHOULD support being mapped anywhere in the 64 bit memory space."
Lgtm