PCIe Integration: do we need a rule about byte enable handling
andreiw opened this issue · 3 comments
andreiw commented
See https://developer.arm.com/documentation/den0029/latest
RS_PCIe_01: The system must support the translation of PE writes with all byte enable patterns to PCIe write requests.
The translation must be done in compliance with PCIe byte enable rules.
ved-rivos commented
The ECM_010 requires the SoC to support naturally aligned 1/2/4 byte writes. Further MMS_030 require supporting all aligned and unaligned access sizes that can be generated by RISC-V application processor harts or endpoints.
andreiw commented
Lgtm