PCIe integration: do we need rules around aligned writes?
andreiw opened this issue · 3 comments
See https://developer.arm.com/documentation/den0029/latest
RS_PCIe_03 The Root Complex must:
• Send 2B PE writes that are 2B aligned as 2B PCIe writes.
• Send 4B PE writes that are 4B aligned as 4B PCIe writes.
• Send 8B PE writes that are 8B aligned as 8B PCIe writes.
RS_PCIe_04 The System must ensure that:
• Aligned 2B writes from Endpoints reach the target as 2B writes.
• Aligned 4B writes from Endpoints reach the target as 4B writes.
• Aligned 8B writes from Endpoints reach the target as 8B writes.
The ECM_010 and MMS_030 were intending to do that. But they can be made more explicit. For ECM_010 will extend the rule to state "One, two, and four byte naturally aligned read and write MUST be supported and lead to a single CfgRd*/CfgWr* transactions of the corresponding size.". For MMS_030, will add "Naturally aligned read and writes of size up to 8 bytes MUST result in a single MemRd/MemWr transactions of the corresponding size."
Lgtm