riscv-software-src/riscv-perf-model

Handling flush in LSU updateIssuePriorityAfterCacheReload

Closed this issue · 4 comments

danbone commented

@h0lyalg0rithm

I'm trying to enable flushing and I'm hitting the assert in this code because the instruction was flushed.

riscv-perf-model/core/LSU.cpp

Lines 1178 to 1196 in e3e1412

void LSU::updateIssuePriorityAfterCacheReload_(const MemoryAccessInfoPtr & mem_access_info_ptr,
const bool is_flushed_inst)
{
const LoadStoreInstIterator & iter = mem_access_info_ptr->getIssueQueueIterator();
sparta_assert(
iter.isValid(),
"Attempt to rehandle cache lookup for instruction not yet in the issue queue! "
<< mem_access_info_ptr);
const LoadStoreInstInfoPtr & inst_info_ptr = *(iter);
// Update issue priority for this outstanding cache miss
if (inst_info_ptr->getState() != LoadStoreInstInfo::IssueState::ISSUED)
{
inst_info_ptr->setState(LoadStoreInstInfo::IssueState::READY);
}
inst_info_ptr->setPriority(LoadStoreInstInfo::IssuePriority::CACHE_RELOAD);
uev_append_ready_.preparePayload(inst_info_ptr)->schedule(sparta::Clock::Cycle(0));
}

Can I just return early if the instruction was flushed?

h0lyalg0rithm commented

@danbone Yes I think that can work.
If spec_load is enabled we might need to either cancel those events or return early in the replay callback
How are you flushing the instructions.

ullahnasr commented

The email knute.lingaard@sfive is no longer valid as Knute lingaard is not at Sifive anymore. He will update his emal address

klingaard commented

Thanks, Nasr. I updated the settings. You (in theory) shouldn't be receiving any more emails.