out-of-order
There are 26 repositories under out-of-order topic.
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
RRZE-HPC/OSACA
Open Source Architecture Code Analyzer
mathis-s/SoomRV
A simple superscalar out-of-order RISC-V microprocessor
riscv-software-src/riscv-perf-model
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
NOP-Processor/NOP-Core
High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
sifferman/labs-with-cva6
Advanced Architecture Labs with CVA6
bcrafton/processor
A compiler, assembler, and processor.
SIMDE-ULL/SIMDE
Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals
DataSystemsGroupUT/Adaptive-Watermarks
An approach to apply concept drifts and ADWIN on the streams event time to reason about the progress of watermarks
RISMicroDevices/RMM4NC30F2X
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
RISMicroDevices/RMR8PM3001A
Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC
CSpyridakis/Tomasulo
Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm
TawfikYasser/Keyed-Watermarks-in-Apache-Flink
Keyed Watermarks in Apache Flink
0mega28/CPU-Simulator
CENOS: The Modern CPU Simulator
mark-i-m/riscy
Superscalar OoO RISCV processor written in Chisel
wh1t3h47/EdgeMailer
EdgeMailer is a tool that tests rate limits of mail providers, it uses libcurl and libuv to make concomitant assynchronous request. This tool is outdated and now is closed source and belongs to YouSendr.
agarwal-ayushi/HPC_Labs
This repository contains the Labs done in the course COL718 High Performance Computing taught by Prof. Sourav Bansal at IIT, Delhi in Fall 2019
AyuubMohamud/Biriq
2-way Out of Order RISC-V Processor
DataSystemsGroupUT/Process-Discovery-over-unordered-streams
A Flink library to implement both a buffer-based and a speculative out-of-order event arrival handlers for online process discovery
gitmehrdad/Superscalar-MIPS
This Verilog implementation represents a 32-bit MIPS processor featuring out-of-order execution.
helcsnewsxd/famaf-computer_science-computer_architecture-lab2
Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
noionion/KaiSui
try to design a Single_Emission_Out-of-Order_Pipeline_RISC-V_Processor
vbogdev/vbn-Riscv
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
wdamron/bitring
Go implementation of a bitmap ring-buffer which tracks the state of windowed out-of-order processing over a sequence of logical offsets
Amutheezan/Tomasulo
Basic Implementation of Tomasulo Algorithm, with memory unit pipelined.
zhuangsc/RFC_marss86
Register file cache implementation on the Marssx86 architectural simulator