riscvarchive/riscv-platform-specs

Issues

• A question about self/cross-modifying code (SMC/CMC)

  #90 opened 2 years ago by zhengxiaolinX
  0

• Eventual completion for vacant memory

  #80 opened 3 years ago by jonmasters
  17

• How to handle non-coherent I/O masters

  #28 opened 3 years ago by jrtc27
  5

• Specify word-size accesses to UART registers

  #88 opened 3 years ago by jhauser-us
  1

• PCI ECAM requirements

  #81 opened 3 years ago by jonmasters
  4

• CLIC requires original basic interrupt mode

  #42 opened 3 years ago by billhuffman
  1

• both CLIC and CLINT seems to be used for the same thing

  #46 opened 3 years ago by kaddkaka
  4

• Server: System Date/Time: Improve explanation for GetTime()

  #58 opened 3 years ago by afaerber
  7

• Inconsistent mtime requirements

  #38 opened 3 years ago by jrtc27
  1

• PCI cache coherency

  #83 opened 3 years ago by jonmasters
  4

• Virtual timers require an offset value

  #82 opened 3 years ago by jonmasters
  1

• I/O ordering requirements (for non-PCIe devices)

  #77 opened 3 years ago by aswaterman
  6

• Missing LICENSE file

  #18 opened 3 years ago by jjscheel
  10

• Adopt the RISC-V documentation format

  #73 opened 3 years ago by jjscheel
  1

• Future interrupt controller of M platform

  #65 opened 3 years ago by henry-hsieh
  0

• relax RAS precise exception on uncorrectable data

  #55 opened 3 years ago by ingallsj
  2

• relax "If Hypervisor extension is supported then the misa.H bit must be writable."

  #54 opened 3 years ago by ingallsj
  2

• Unnecessary/Inappropriate documentation of kernel address space decisions

  #13 opened 3 years ago by jrtc27
  9

• RVM platform requirements

  #25 opened 3 years ago by tovine
  1

• Hypervisor guard hole

  #5 opened 6 years ago by fintelia
  4