Pinned Repositories
educational-materials
Educational materials for RISC-V
risc-v-getting-started-guide
The official RISC-V getting started guide
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
riscv-gcc
riscv-go
riscv-linux
RISC-V Linux Port
riscv-qemu
QEMU with RISC-V (RV64G, RV32G) Emulation Support
riscv-software-list
The RISC-V software tools list, as seen on riscv.org
riscv-v-spec
Working draft of the proposed RISC-V V vector extension
riscv-wiki
RISC-V Archive's Repositories
riscvarchive/riscv-v-spec
Working draft of the proposed RISC-V V vector extension
riscvarchive/riscv-gcc
riscvarchive/risc-v-getting-started-guide
The official RISC-V getting started guide
riscvarchive/riscv-code-size-reduction
riscvarchive/riscv-binutils-gdb
RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
riscvarchive/riscv-platform-specs
RISC-V Profiles and Platform Specification
riscvarchive/riscv-newlib
RISC-V port of newlib
riscvarchive/riscv-tee
riscvarchive/riscv-zicond
The ISA specification for the ZiCondOps extension.
riscvarchive/riscv-dejagnu
DejaGnu RISC-V port
riscvarchive/riscv-zfinx
riscvarchive/riscv-alt-fp
RISC-V Alternate FP Format
riscvarchive/riscv-zacas
riscv-zacas created from docs-spec-template template
riscvarchive/rvm-csi
Group administration repository for SIG: RISC-V Common Software Interface (RVM-CSI)
riscvarchive/riscv-svadu
The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.
riscvarchive/riscv-zawrs
The repo will be used to hold the draft Zawrs (fast-track) extension and to make releases for reviews.
riscvarchive/riscv-time-compare
riscvarchive/blockchain
Blockchain SIG Community
riscvarchive/cache-management-ops
RISC-V CMOs Charter, Minutes, Agendas, Etc
riscvarchive/riscv-indirect-csr-access
Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.
riscvarchive/riscv-smcntrpmf
Cycle & Instret Privilege Mode Filtering Architecture Extension
riscvarchive/riscv-state-enable
riscvarchive/riscv-smcdeleg-ssccfg
Supervisor Counter Delegation Architecture Extension
riscvarchive/automotive
Group administration repository for SIG: Automotive
riscvarchive/control-transfer-records
Group administration repository for SIG: Control Transfer History
riscvarchive/documentation
Group administration repository for SIG: Documentation
riscvarchive/riscv-ras-terms-defs
The RAS Terms & Definitions specification define the terms and definitions for physical mechanisms starting from common ones from research and development to adapting the terms as needed.
riscvarchive/unified-discovery
riscvarchive/bfloat16
riscvarchive/ras-terms-defs
Group administration repository for Tech: RAS Terms and Definitions