riscvarchive/riscv-qemu

Generate illegal instruction traps for s* CSR accesses if misa.S is not set

michaeljclark opened this issue · 0 comments

michaeljclark commented

misa.S indicates the machine supports S mode, and hence implements the s*CSRs, either returning the required values, or hard-coded to zero as specified.

However, if S-mode is not implemented, s* CSR accesses should generate illegal instruction traps.