riscvarchive/riscv-qemu

can't execute rdtime instruction

LoveZJT opened this issue · 1 comments

Why qemu-system-riscv32 executing rdtime instruction will cause illegal instruction exception, while rdcycle and rdinstret are right.

I believe that on rocket, rdtime traps into machine mode which then emulates the instruction. I know that this is true for most if not all SiFive cores. So qemu is just faithfully implementing exactly what the hardware does. SiFive platforms have a MMIO timer register that you may be able to read directly, which is faster than using rdtime, because rdtime traps.