Pinned Repositories
Algos
Implementation of well-known (and some rare) algorithms, mostly in C++
eu1er
ghdl
VHDL 2008/93/87 simulator
JSON2RTLRegFile
Generate RTL/Doc files from register description in JSON
neomake
Async :make and linting framework for Neovim/Vim
OSVVM
Open Source VHDL Verification Methodology (OSVVM) Repository
systemrdl
SystemRDL Compiler
systemrdl-compiler
Tool to generate synthesizable RTL files from SystemRDL input
vcdvcd
Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line viewer.
VHDL-indent-93-syntax
Revised VHDL indent file
robinkjoy's Repositories
robinkjoy/systemrdl-compiler
Tool to generate synthesizable RTL files from SystemRDL input
robinkjoy/JSON2RTLRegFile
Generate RTL/Doc files from register description in JSON
robinkjoy/systemrdl
SystemRDL Compiler
robinkjoy/Algos
Implementation of well-known (and some rare) algorithms, mostly in C++
robinkjoy/eu1er
robinkjoy/ghdl
VHDL 2008/93/87 simulator
robinkjoy/neomake
Async :make and linting framework for Neovim/Vim
robinkjoy/OSVVM
Open Source VHDL Verification Methodology (OSVVM) Repository
robinkjoy/vcdvcd
Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line viewer.
robinkjoy/VHDL-indent-93-syntax
Revised VHDL indent file
robinkjoy/VHDLComp
Vim Plugin to convert VHDL entity to component, signals or instantiations
robinkjoy/vim-snippets
vim-snipmate default snippets (Previously snipmate-snippets)