ruishihan

ruishihan's Stars

• olofk/ipyxact

  Python-based IP-XACT parser

  Language:Python12648

• tudortimi/rgen

  IP-XACT based register generator

  Language:Mako94

• edaa-org/pyEDAA.IPXACT

  An IP-XACT DOM for IEEE 1685-2014 in Python.

  Language:Python1911

• freechipsproject/chisel-testers

  Provides various testers for chisel users

  Language:Scala10150

• ucb-bar/chiseltest

  The batteries-included testing and formal verification library for Chisel-based RTL designs.

  Language:Scala22776

• bitcoin/bitcoin

  Bitcoin Core integration/staging tree

  Language:C++80.9k36.4k

• latelee/H264BSAnalyzer

  H264(AVC) and H265(HEVC) bit stream Analyzer, VS2010 MFC project(Windows 7 x64).

  Language:C852340

• chipsalliance/rocket-chip

  Rocket Chip Generator

  Language:Scala3.3k1.1k

• chipsalliance/treadle

  Chisel/Firrtl execution engine

  Language:Scala15331

• freechipsproject/firrtl-interpreter

  A scala based simulator for circuits described by a LoFirrtl file

  Language:Scala4723

• freechipsproject/diagrammer

  Provides dot visualizations of chisel/firrtl circuits

  Language:Scala11820

• XUANTIE-RV/wujian100_open

  IC design and development should be faster，simpler and more reliable

  Language:Verilog1.9k573

• SpinalHDL/SpinalHDL

  Scala based HDL

  Language:Scala1.7k336

• SpinalHDL/VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  Language:Assembly2.5k421

• ruishihan/yosys

  Yosys Open SYnthesis Suite

  1

• ruishihan/riscv-boom

  BOOM: Berkeley Out-of-Order Machine

  1

• freechipsproject/chisel-bootcamp

  Generator Bootcamp Material: Learn Chisel the Right Way

  Language:Jupyter Notebook993280

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.6k894

• chipsalliance/firrtl

  Flexible Intermediate Representation for RTL

  Language:Scala732177

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala4.1k607

• riscv/riscv-opcodes

  RISC-V Opcodes

  Language:Python706306

• sifive/last-week-in-risc-v

  Weekly RISC-V Newsletter

  Language:Shell284

• ruishihan/documents-1

  riscv.github.io

  1

• westerndigitalcorporation/pyvcd

  Python package for writing Value Change Dump (VCD) files.

  Language:Python11041

• m-labs/nmigen

  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

  Language:Python66257

• PyHDI/Pyverilog

  Python-based Hardware Design Processing Toolkit for Verilog HDL

  Language:Python649183

• myhdl/myhdl

  The MyHDL development repository

  Language:Python1.1k248

• kevinpt/symbolator

  HDL symbol generator

  Language:Python18649

• m-labs/migen

  A Python toolbox for building complex digital hardware

  Language:Python1.2k211

• gauravtewari/python-to-verilog

  Generate a Verilog Source file and testbench file for a given Moore FSM

  Language:Python174