russdill/bch_verilog

Issues

• key_ready used before declared.

  #9 opened 2 years ago by mgjaggers
  0

• BCH Encoder Different result from MATLAB

  #8 opened 3 years ago by h-sh-h
  1

• Literature about the bch

  #7 opened 3 years ago by wzu0
  1

• can not find corrent files

  #6 opened 3 years ago by wzu0
  3

• Makefile.xilinx - nothing to be done for 'all'

  #5 opened 4 years ago by pacikk
  1

• modelsim simulation compile error

  #4 opened 5 years ago by chinafpga
  1

• Detection of un-correctable errors

  #3 opened 6 years ago by AEW2015
  1

• Regression, especially for large values of T

  #2 opened 9 years ago by russdill
  0