Issues
- 5
`riscv`: Add macro to define CSR register types
#218 opened by rmsyn - 3
`riscv`: Consider strategy for exception safe code
#212 opened by rmsyn - 2
RFC: Platform-specific exception codes
#146 opened by SoulSharer - 5
- 5
- 1
- 1
`riscv`: Pub macros for non-standard CSRs
#187 opened by dreiss - 1
`riscv-rt`: link.x expected filename pattern
#202 opened by roby2014 - 1
`riscv`: Support more fence variants
#193 opened by jsgf - 1
`riscv-rt`: Machine + Supervisor mixed executable
#192 opened by ZhekaS - 3
`riscv-rt`: Broken eh_frame relocations on QEMU
#196 opened by dreiss - 1
`riscv-rt`: Duplicate symbol when linking with Newlib
#197 opened by gmmyung - 1
- 0
`riscv-rt`: Prune unused symbols
#155 opened by piegamesde - 2
`riscv-rt`: Pre initialization trap handling
#156 opened by piegamesde - 1
`riscv-rt`: Assembly algorithm for RAM init incompatible with upcoming RVE extension (future proofing)
#189 opened by hegza - 12
`riscv-peripheral`: add standard peripherals
#124 opened by romancardenas - 5
`riscv-rt`: Using this as a library?
#154 opened by hyperswine - 1
Why are `asm::fence` and `asm::fence_i` unsafe?
#179 opened by jsgf - 5
`riscv-rt`: LLVM raises spurious errors in release mode for instructions of ISA extensions (e.g., M or E)
#175 opened by daniestevez - 0
`riscv-rt`: nightly builds fail with `single-hart` feature: linker needs `default_mp_hook` symbol
#182 opened by romancardenas - 1
- 2
Release time
#173 opened by romancardenas - 1
`riscv`: `interrupt::free()` for Supervisor Mode
#114 opened by FawazTirmizi - 14
`riscv-rt`: Implement FPU initialization
#157 opened by Disasm - 3
- 0
`riscv`: Add missing CSR's
#1 opened by dvc94ch - 2
FCSR operations generally cannot be used from Rust
#148 opened by RalfJung - 2
RVXXI registers
#60 opened by Skallwar - 2
Replace bors with GitHub merge queues
#133 opened by romancardenas - 4
`sip` register set / clear functions
#130 opened by PitiBouchon - 1
create a release for the atomicity things
#119 opened by orangecms - 3
RISCV sdk with RUST support
#92 opened by AchyuthAGNA5675 - 1
tag the 0.9.0 release
#118 opened by orangecms - 3
The `critical_section` implementation is wrong
#116 opened by Tnze - 1
- 1
The MTIP bit in mip register is read-only
#62 opened by SKTT1Ryze - 6
Support for riscv32imc.
#100 opened by mgaggero - 2
Implementing PMP registers as an array?
#74 opened by jwnhy - 2
"cannot link object files with different floating-point ABI" rustc 1.56.0-nightly (2021-08-06)
#85 opened by o8vm - 9
linking with `rust-lld` failed: no memory region specified for section '.eh_frame', on Ubuntu 16 i686
#59 opened by advancedwebdeveloper - 1
- 1
Supervisor level ISA (Page system) support
#39 opened by luojia65 - 2
Mcounteren Missing
#56 opened by dkhayes117 - 2
How to use mcause::read()
#55 opened by dkhayes117 - 4
Set Stack Pointer and Return Address
#54 opened by dkhayes117 - 2
rust cross compile to riscv64gc
#27 opened by H-Y-B - 3
move plic definition to riscv crate
#2 opened by dvc94ch - 6
Raw instruction functions are unsafe footguns
#11 opened by strake - 1
Failure to build due to unreachable code
#3 opened by aaazalea