saibhargav5

saibhargav5's Stars

• ARC-Lab-UF/sv-tutorial

  SystemVerilog Tutorial

  Language:SystemVerilog1198128

• dadongshangu/async_FIFO

  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

  Language:SystemVerilog562215

• zli87/Wishbone-to-I2C-bus-controller-IP-Verification

  ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.

  Language:VHDL17105

• anishagartia/Tomasulo-Algorithm

  Implementation of Tomasulo Algorithm for Pipelined Processor (Computer Architecture)

  Language:C++12308

• Milleraj66/ECE585_TomasuloAlgorithm

  C++ Tomasulo Algorithm Simulator

  Language:C++102037

• abhishekjain1991-zz/Out-of-Order-Superscalar-processor-simulator

  Implemented a Superscalar Processor with Out-of-Order execution using Tomasulo Dynamic Instruction Scheduling algorithm. The project involved simulating all pipeline stages of the processor. Experiments were also carried out to obtain the optimum processor configuration for the best IPC (Instructions Per Cycle) value.

  Language:C++1100

• OmarElayat/Tomasulo_Algorithm_Architectural_Simulator

  C++ architectural simulator capable of assessing the performance of a simplified superscalar out-of-order dual-issue 16-bit RISC processor that uses Tomasulo’s algorithm with speculation

  Language:C++1100