saipavanace

saipavanace's Stars

• rggen/rggen

  Code generation tool for control and status registers

  Language:Ruby34544

• chiggs/UVM

  Mirror of the Universal Verification Methodology from sourceforge

  Language:SystemVerilog3312

• cristian-mattarei/CoSA

  CoreIR Symbolic Analyzer

  Language:Python6215

• ayushgarg31/Ask-Questions---Django-based-website

  Language:CSS71

• eirikpre/VSCode-SystemVerilog

  SystemVerilog support in VS Code

  Language:TypeScript13250

• dalance/svlint

  SystemVerilog linter

  Language:Rust32435

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k217

• fvutils/pyvsc

  Python packages providing a library for Verification Stimulus and Coverage

  Language:Python11526

• ml-tooling/best-of-ml-python

  🏆 A ranked list of awesome machine learning Python libraries. Updated weekly.

  18.7k2.6k

• Nic30/hdlConvertor

  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

  Language:C++28568

• PXVI/prune_uvmg

  GUI based UVM Test Environment generation tool

  Language:Python81

• SeanOBoyle/DoxygenFilterSystemVerilog

  Language:Perl3510

• ben-marshall/verilog-vcd-parser

  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

  Language:C++9136

• Freecellera/freecellera-uvm

  Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)

  Language:SystemVerilog103

• kevinpt/symbolator

  HDL symbol generator

  Language:Python18649

• TheClams/SystemVerilog

  SystemVerilog plugin for Sublime Text

  Language:Python4617

• myhdl/myhdl

  The MyHDL development repository

  Language:Python1.1k248

• tpoikela/uvm-python

  UVM 1.2 port to Python

  Language:Python24546

• alpacahq/example-scalping

  A working example algorithm for scalping strategy trading multiple stocks concurrently using python asyncio

  Language:Python776185

• StockSharp/StockSharp

  Algorithmic trading and quantitative trading open source platform to develop trading robots (stock markets, forex, crypto, bitcoins, and options).

  Language:C#7.5k1.8k

• SravB/Algorithmic-Trading

  Algorithmic trading using machine learning.

  Language:Python11374

• doncat99/StockRecommendSystem

  An intelligent recommender system for stock analyzing, predicting and trading

  Language:Python14169

• pskrunner14/trading-bot

  Stock Trading Bot using Deep Q-Learning

  Language:Jupyter Notebook1k345

• yacoubb/stock-trading-ml

  A stock trading bot that uses machine learning to make price predictions.

  Language:Python626258

• rlee287/hardware-bus-infrastructure

  A collection of formal properties for hardware buses, and cores using them.

  Language:Verilog4

• aleek/mc68851

  Verilog implementation of MC68851 Memory Management Unit

  Language:Verilog82

• tej-chavan/Design-and-Verification-of-DDR3-Memory-Controller

  The memory model was leveraged from micron.

  Language:SystemVerilog2216

• stffrdhrn/sdram-controller

  Verilog SDRAM memory controller

  Language:Verilog31395

• chiselverify/chiselverify

  A dynamic verification library for Chisel.

  Language:Scala14223

• cnrv/rocket-chip-read

  Comment on the rocket-chip source code

  16944