samitbasu/rust-hdl

Issues

• Correct way to drive inputs?

  #43 opened 4 months ago by Necromaticon
  1

• Support for Sipeed Tang Nano 9K FPGA Development Board Gowin GW1NR-9 RISC-V HDMI (Tang Nano 9k)

  #41 opened 7 months ago by Cr0a3
  6

• Feature Request: add support for running VHDL/Verilog code alongside/within RustHDL

  #42 opened 6 months ago by parker-research
  0

• Support for BeagleV-Fire

  #33 opened a year ago by jimkring
  1

• Generic constants propagate to Verilog output

  #39 opened 7 months ago by dankirkham
  1

• QUESTION: How does array indexing work with non-literal indices?

  #38 opened 9 months ago by john-terrell
  1

• QUESTION: Arithmetic shift right?

  #37 opened 9 months ago by john-terrell
  1

• QUESTION: How to concat bit values together?

  #36 opened 9 months ago by john-terrell
  1

• How does this project works? Any papers or docs?

  #35 opened a year ago by myrfy001
  1

• Request: VHDL output

  #34 opened a year ago by tschinz
  0

• Why rename?

  #32 opened a year ago by alexpyattaev
  0

• Dumping BRAM Contents in Simulation

  #31 opened a year ago by ThePerfectComputer
  4

• Calling `Simulation::add_testbench` multiple times makes the simulations interfere with each other

  #30 opened a year ago by PoignardAzur
  3

• Naming a signal "output" triggers a "custom attribute panicked" error message

  #29 opened a year ago by PoignardAzur
  1

• Update svg dependency

  #28 opened a year ago by PoignardAzur
  0

• rust-hdl and circt

  #25 opened a year ago by jcdutton
  2

• Incorrect Verilog Output

  #22 opened a year ago by mwbryant
  5

• Use default on LogicState

  #26 opened a year ago by samitbasu
  0

• surface nextpnr errors during build

  #21 opened 2 years ago by kpwebb
  1

• Support match expressions

  #24 opened a year ago by twitzelbos
  0

• Support Sum Types

  #23 opened a year ago by ThePerfectComputer
  2

• Document the PWM device

  #20 opened 2 years ago by samitbasu
  0

• Documentation issue

  #19 opened 2 years ago by samitbasu
  0

• What's the right way to get `posedge` to appear in this Verilog output?

  #16 opened 2 years ago by Boscop
  3

• Rework RustHDL docs

  #13 opened 2 years ago by samitbasu
  0

• Add nextpnr-ice40 support for alchitry cu

  #14 opened 2 years ago by samitbasu
  0

• Support for multidimensional packed bit array

  #12 opened 2 years ago by explocion
  7

• Logical shift left using Bits<> of different widths doesn't compile

  #7 opened 2 years ago by john-terrell
  2

• Arithmetic shift right not compiling

  #8 opened 2 years ago by john-terrell
  2

• Question about the generated verilog file

  #5 opened 2 years ago by AdiwenaPutra
  2

• Inline signed conversions don't compile.

  #2 opened 2 years ago by john-terrell
  3

• Add Fixed point the support to RustHDL. Similar to the support in FIRRTL.

  #4 opened 2 years ago by samitbasu
  0

• Request: Output FIRRTL as well as Verilog

  #3 opened 2 years ago by john-terrell
  0

• Request: support for enum discriminants

  #1 opened 2 years ago by john-terrell
  1