This project is an example of automating Vivado and its SDK to exercise an emulated JTAG TAP controller. It takes a synthesized TAP core, instantiates in a test harness that is driven by a CPU macro on the FPGA, and builds of bitstream for that design (DUT + test harness). From that point, SDK automation is used to build firmware that stimulates the DUT according to user commands received over UART. Finally, a small Python program is used to send UART commands and check the result.
As a result, this project covers a variety of features in Vivado + SDK workflow that are relevant to text-based designs under revision control:
- Describing a Vivado project with TCL commands rather than an XPR file.
- Importing pre-synthesized logic (EDIF / EDF)
- Creating a block diagram for a CPU macro and AXI peripherals using TCL, rather than using a BRD file.
- Instantiating a CPU macro in user-written RTL.
- Writing firmware that interacts with an AXI GPIO block connected to the CPU macro.
- Writing firmware that reads and reacts to commands received over UART.
- SDK automation to build firmware (ELF)
- SDK automation to program the FPGA and CPU macro.
- You'll need a Zynq FPGA board. I've tested this example with PYNQ-Z1 and ZC702 boards, but it should run on other Zynq boards, too.
- Make sure that you have installed Vivado and its SDK. Sample instructions are here. If you're not using the PYNQ-Z1 board, you can skip the part about installing PYNQ board files. (These instructions have been tested with Xilinx Unified 2020.1)
- Generate an EDIF for the TAP core. Sample instructions are here.
- Set these environment variables:
FPGA_BOARD
: Choose from options listed inget_board_parts
in the Vivado TCL console.FPGA_PART
: Choose from options listed inget_parts
in the Vivado TCL console.TAP_CORE_LOC
: Absolute path to the EDIF file for the TAP core.UART_DEV_NAME
: Name of the USB serial device (e.g.,/dev/ttyUSB0
)
- Build the FPGA bitstream:
> vivado -mode batch -source tcl/vivado.tcl
- Copy over firmware files into the SDK work directory:
> mkdir -p project/project.sdk/sw
> cp -r firmware project/project.sdk/sw/src
- Build the firmware:
> xsct -source tcl/sdk.tcl
- Program the bitstream and firmware and start the program:
> xsct -batch -source tcl/program.tcl
- Interact with CPU over UART (need Python 3.7+ with
pyserial
installed)
> python uart_test.py