shanyinshuiyue's Stars
daviddhas/Some-useful-Perl-Scripts
These scrpits will be extremly useful in parsing Verilog files
ngageoint/MATLAB_SAR
A basic MATLAB library to demonstrate reading, writing, display, and simple processing of complex SAR data using the NGA SICD standard.
pdollar/toolbox
Piotr's Image & Video Matlab Toolbox
FreeRTOS/FreeRTOS
'Classic' FreeRTOS distribution. Started as Git clone of FreeRTOS SourceForge SVN repo. Submodules the kernel.
justjavac/free-programming-books-zh_CN
:books: 免费的计算机编程类中文书籍,欢迎投稿
HelenOS/helenos
A portable microkernel-based multiserver operating system written from scratch.
cdoco/learn-regex-zh
:cn: 翻译: 学习正则表达式的简单方法
wkoszek/libxbf
Xilinx Bitstream Format Library. Easily read .bit files from C programs.
lnis-uofu/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
lnis-uofu/OpenFPGA
An Open-source FPGA IP Generator
YosysHQ/nextpnr
nextpnr portable FPGA place and route tool
librecores/librecores-web
LibreCores Web Site
ziishaned/learn-regex
Learn regex the easy way
hdl4fpga/hdl4fpga
VHDL library 4 FPGAs
f32c/f32c
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
FPGAwars/FPGA-peripherals
:seedling: :snowflake: Collection of open-source peripherals in Verilog
intel/aib-phy-hardware
huaweicloud/huaweicloud-fpga
The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.
zlgopen/awtk
AWTK = Toolkit AnyWhere(a cross-platform embedded GUI)
mjijeesh/Core8051s
caj2pdf/caj2pdf
Convert CAJ (China Academic Journals) files to PDF. 转换**知网 CAJ 格式文献为 PDF。佛系转换,成功与否,皆是玄学。
slaclab/ruckus
Vivado build system
byuccl/tincr
A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite
f4pga/prjxray
Documenting the Xilinx 7-series bit-stream format.
osqzss/gps-sdr-sim
Software-Defined GPS Signal Simulator
jlevy/the-art-of-command-line
Master the command line, in one page
jwwebbopen/VHDLTools
Tools to facilitate VHDL design
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
keon/algorithms
Minimal examples of data structures and algorithms in Python
bluespec/Piccolo
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)