shili2017

Sleep every day!

Carnegie Mellon UniversityPittsburgh

Pinned Repositories

CherrySprings
Language:Scala17 0 12
Zhoushan
Open Source Chip Project by University (OSCPU) - Zhoushan Core
Language:Scala44 1 09
connect
CONNECT: CONfigurable NEtwork Creation Tool
Language:Bluespec1 0 01
CONNECT-AXI
Language:Verilog3 1 00
NutShell-on-CONNECT
NutShell on CONNECT NoC
Language:Scala0 0 00
rcc
rCore in C
Language:C6 0 13
RISC-V-All-Aboard-zh-cn
Sifive All Aboard 系列文章翻译
8 1 00
shili2017.github.io
Language:Shell1 0 00
VV214-Project
UM-SJTU JI 2019SP VV214 (Linear Algebra) Group 11 Final Project
Language:MATLAB1 0 01
Ria
UM-SJTU JI VE450 2021 Summer Capstone Design Project
Language:SystemVerilog101

shili2017's Repositories

shili2017/RISC-V-All-Aboard-zh-cn
Sifive All Aboard 系列文章翻译
8 1 00
shili2017/rcc
rCore in C
Language:C6 0 13
shili2017/CONNECT-AXI
Language:Verilog3 1 00
shili2017/connect
CONNECT: CONfigurable NEtwork Creation Tool
Language:Bluespec1 0 01
shili2017/shili2017.github.io
Language:Shell1 0 00
shili2017/VV214-Project
UM-SJTU JI 2019SP VV214 (Linear Algebra) Group 11 Final Project
Language:MATLAB1 0 01
shili2017/NutShell-on-CONNECT
NutShell on CONNECT NoC
Language:Scala0 0 00
shili2017/Ria
UM-SJTU JI VE450 2021 Summer Capstone Design Project
Language:SystemVerilog0 0 00
shili2017/riscv-tests
Language:C0 0
shili2017/rocket-chip-inclusive-cache
An RTL generator for a last-level shared inclusive TileLink cache controller
Language:Scala0 0
shili2017/shili2017
0 1