shili2017

shili2017's Stars

• mpaland/printf

  Tiny, fast, non-dependent and fully loaded printf implementation for embedded systems. Extensive test suite passing.

  Language:C2.5k7599455

• shining1984/PL-Compiler-Resource

  程序语言与编译技术相关资料（持续更新中）

  2k815260

• flame/how-to-optimize-gemm

  Language:C1.7k4517351

• tangx/Stop-Ask-Questions-The-Stupid-Ways

  Stop-To-Ask-Questions-The-Stupid-Ways

  96173289

• sampsyo/cs6120

  advanced compilers

  Language:HTML71220124157

• michaeljclark/rv8

  RISC-V simulator for x86-64

  Language:C++668445997

• crossroadsfpga/pigasus

  100Gbps Intrusion Detection and Prevention System

  Language:C++664341474

• PrincetonUniversity/openpiton

  The OpenPiton Platform

  Language:Assembly6145763211

• THU-DSP-LAB/ventus-gpgpu

  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

  Language:Scala507132363

• WangXuan95/BSV_Tutorial_cn

  一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

  Language:Bluespec48192540

• PacktPublishing/Learn-LLVM-12

  Learn LLVM 12, published by Packt

  Language:C++4731217102

• CMU-HKN/CMU-ECE-CS-Guide

  How to survive CMU as an ECE/CS major

  457136119

• bluespec/Piccolo

  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

  Language:Verilog301242648

• booksim/booksim2

  BookSim 2.0

  Language:C++2482828157

• ucb-bar/constellation

  A Chisel RTL generator for network-on-chip interconnects

  Language:Scala156173622

• sparcians/map

  Modeling Architectural Platform

  Language:C++1521820653

• hehao98/RISCV-Simulator

  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation

  Language:C++1515330

• cyyself/cemu

  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education and research.

  Language:C++93537

• arch-simulator-sig/advanced-computer-architecture

  体系结构研讨 + ysyx高阶大纲 (WIP

  88226

• nbdd0121/r2vm

  Rust RISC-V Virtual Machine

  Language:Rust83739

• sifive/block-inclusivecache-sifive

  Language:Scala7111845

• litmus-tests/litmus-tests-riscv

  RISC-V architecture concurrency model litmus tests

  Language:Assembly6791420

• Superscalar-HIT-Core/Superscalar-HIT-Core-NSCSCC2020

  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog

  Language:SystemVerilog43405

• adsc-hls/synthesizable_h264

  A Synthesizable implementation of H.264 Video Decoding

  Language:C291205

• jianyicheng/DSS

  DASS HLS Compiler

  Language:VHDL26318

• ACANETS/dpcpp-tutorial

  Lectures and Labs for Data Parallel Computing and DPC++. Sponsored by Intel Corporation.

  Language:C++11506

• UMJI-VE450-21SU/Ria

  UM-SJTU JI VE450 2021 Summer Capstone Design Project

  Language:SystemVerilog10101

• yqszxx/yars

  YARS - Yet Another RISC-V Simulator

  Language:Go7210

• ZimingYuan/testos

  A simple Riscv operating system in C refering to rCore-tutorial-v3.

  Language:Python7311

• yqszxx/yarc

  YARC - Yet Another RISC-V Chip

  Language:Scala5200