Superscalar-HIT-Core/Superscalar-HIT-Core-NSCSCC2020
a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
SystemVerilog
Stargazers
- 14010007517Chongqing University
- afterCherry
- antsmnTurin, Italy
- Bohan-huHKUST(GZ)
- CaptainSlowWZY
- chenhy0106Beijing
- cheungxi
- chiro2001Harbin Institute of Technology, Shenzhen
- chnjstyj
- ChrisqcwxHarbin Institution of Technology (Shenzhen)
- ChufanSukiZhejiang, China
- codefuturedalaoWuhan University
- davidli1515
- dzwduanInstitute of Computing Technology, CAS
- enkerewpoPeking University
- ipChrisLeeByteDance
- KuangjuXUCAS
- lcp29HITsz
- mfkiwl
- monikerzju
- NorbertZhengPeking University
- nothatDinger
- RickyTino@hitwh-nscscc
- risingstar213Huazhong University of Science and Technology
- shen-wenxin
- shili2017Carnegie Mellon University
- SunflowerAriesFudan University
- UJAnn00628
- victoryang00Baskin Engineering
- willson0v0HITSZ
- Xiao-li-He
- XuYipei
- xzcxzcyySJTU
- yuechen-sysKAIST
- YuntaiLeo
- zscBeijing